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NET2
- This file with the wavelet transf Mallat implementation of wavelet Verilog hdl code modules for radi Modelsim 6.6 crack, can be used f A written using Verilog DDR2 cont Simple CPU VHDL implementation an Dual-port RAM design, usi
SOU
- 这是用C写的正弦函数定点数据生成代码,内容是生成verilog中RAM或者ROM和Matlab处理时的所用的数据。-It is written with C fixed-point data generate code sine function, the content is generated verilog RAM or ROM, and Matlab in the processing of the data used.
ad-ram
- ad采样 通过fpga 传输给ram-ad fpga ram verilog
ram
- 利用verilog实现的双口RAM。文件包含工程文件,仿真文件,使用方便。-Using verilog implementation of dual-port RAM. File contains the project files, simulation files, easy to use.
FIFO-verilog
- 本实验完成的是8位异步FIFO的设计,其中写时钟100MHz,读时钟为5MHz,其中RAM的深度为256。当写时钟脉冲上升沿到来时,判断写信号是有效,则写一个八位数据到RAM中;当读时钟脉冲上升沿到来时,判断读信号是有效,则从RAM中把一个八位数据读出来。当RAM中数据写满时产生一个满标志,不能再往RAM再写数据;当RAM中数据读空时产生一个空标志,不能再从RAM读出数据。-In this study, completed the 8-bit asynchronous FIFO design,
ram
- 基于FPGA的rom程序(verilog)-rom procedure
RAM
- 基于verilog的双口和单口RAM的实现-Verilog dual port and single port RAM-based implementation
verilog-code
- 都是verilog代码:多路选择器代码,储存器代码,时钟分频器代码,串并转换电路代码,香农扩展运算代码,ram代码。-MUX code and REGISTER code clock divider code string conversion circuit code, Shannon extended op code, the ram code.
verilog--sram
- ram的fpga应用,用verilog语言实现,适用于cyclone 2系列-ram the fpga application verilog language applicable to cyclone 2
dual ram
- 此文件是FPGA工程文件,包含了dualram的设计代码和testbench代码,使用了verilog hdl编写,仿真结果符合设计要求。
Verilog
- RAM ,IFFO实现字节的存储器设计,经过验证-RAM, IFFO bytes of memory design, proven
RAM
- 通过使用fpga,verilog语言来实现RAM的读写功能。-for ram reading and writing
verilog
- verilog 常用模块,包含设计模块和测试模块,如有ram, lifo等-verilog useful blocks
RAM
- Nios ii双口ram,用于MCU通过nios ii进行双口ram通信,verilog格式.-Nios II dual port RAM, for MCU dual port RAM communication, through the Nios II Verilog format.
DULE-RAM
- 基于VERILOG的双口ram例子,比较简单,不是很复杂,入门了解就可以了。-Based on dual port ram VERILOG example, the relatively simple, not very complicated, entry understand it.
RAM
- 用verilog实现了IP核的使用,例化了一个RAM,用来进行读写操作,另外还编写了斐波那契数列来进行测试。-Using verilog to achieve the use of IP core, the instantiation of a RAM, used to read and write operations, in addition to the preparation of the Fibonacci sequence for testing.
fpga
- pid算法控制电机运动,实现fpga与dsp的双口RAM通信(PID algorithm to control motor movement, the realization of FPGA and DSP dual port RAM communication)
pudn
- Encoders, decoders and RAM Model
各种基础module打包下载全集
- 例如分频器,alu,ram的verilog实现(The implementation of divider, alu, ram etc. in verilog)
ARM_SOC
- ARM最小系统,vivado或ISE综合后下载至FPGA板子上可以做ARM用,包含连接在AHB总线上的RAM和ROM,ARM内核引出JTAG接口,可以连接调试器用keil-MDK进行调试!(ARM minimum system, vivado or ISE integrated download to the FPGA board can be used as ARM, including the RAM and ROM connected to the AHB bus, the ARM ker